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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
May 2007
FSQ100 Green Mode Fairchild Power Switch (FPSTM)
Features
Internal Avalanche-Rugged SenseFET Precision Fixed Operating Frequency (67KHz) Burst-Mode Operation Internal Start-up Circuit Pulse-by-Pulse Current Limiting Over-Voltage Protection (OVP) Overload Protection (OLP) Internal Thermal Shutdown Function (TSD) Auto-Restart Mode Under-Voltage Lockout (UVLO) with Hysteresis Built-in Soft Start Secondary-Side Regulation
Description
The FSQ100 consists of an integrated Pulse Width Modulator (PWM) and SenseFET, specifically designed for high-performance, off-line, Switch-Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high-voltage power switching regulator that combines a VDMOS SenseFET with a voltage mode PWM control block. The integrated PWM controller features include a fixed oscillator, Under-Voltage Lockout (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shutdown (TSD) protection, and temperature-compensated precision-current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC solution, the FSQ100 device reduces total component count and design size and weight, while increasing efficiency, productivity, and system reliability. This device provides a basic platform well suited for cost-effective flyback converters.
Applications
Charger & Adapter for Mobile Phone, PDA, MP3 Auxiliary Power for White Goods, PC, C-TV, Monitor
Related Application Notes
AN-4137 Design Guidelines for Off-line Flyback Converters using FPSTM AN-4141 Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147 Design Guidelines for RCD Snubber of Flyback AN-4134 Design Guidelines for Off-line Forward Converters using FPSTM AN-4138 Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPSTM)
Ordering Information
Product Number
FSQ100
Package
8-DIP
Marking Code
Q100
BVDSS
650V
fOSC
67KHz
RDS(ON)
16
FPSTM is a trademark of Fairchild Semiconductor Corporation.
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
www.fairchildsemi.com
FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Typical Application
AC IN
OUTPUT POWER TABLE
DC OUT
Open Frame(1) Product 230VAC 15%(2)
13W
85~265VAC
8W
Vstr PWM Vfb
Drain
FSQ100
GND
VCC
Notes: 1. Maximum practical continuous power in an openframe design with sufficient drain pattern as a heat sinker, at 50C ambient. 2. 230VAC or 100/115VAC with doubler.
Figure 1.
Typical Flyback Application
Internal Block Diagram
Vstr 5 V CC 2 UVLO Voltage Ref Internal Bias 9/7V Idelay 5A Ifb 400A Vck OSC PWM Vfb 3 S/S 15ms BURST VBURL/ VBURH NC 4 Reset VSD OVP TSD A/R 1 GND OLP SQ R LEB ILIM Vth DRIVER SQ R SFET L H Drain 6,7,8
Rsense
Min.20V
Figure 2.
Functional Block Diagram
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Pin Assignments
GND Vcc Vfb NC
1 2 3 4
8 7 6 5
Drain Drain Drain Vstr
Figure 3.
Pin Configuration (Top View)
Pin Definitions
Pin #
1
Name
GND
Description
Ground. SenseFET source terminal on primary side and internal control ground. Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during start-up (see Figure 2). When VCC reaches the UVLO upper threshold (9V), the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. Feedback. Inverting input to the PWM comparator with its normal input level lies between 0.5V and 2.5V. It has a 0.4mA current source connected internally, while a capacitor and optocoupler are typically connected externally. A feedback voltage of 4.5V triggers overload protection (OLP). There is a time delay while charging external capacitor Cfb from 3V to 4.5V using an internal 5A current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate in true overload conditions. No Connection. Start-up. This pin connects directly to the rectified AC line voltage source. At start-up, the internal switch supplies internal bias and charges an external storage capacitor placed between the VCC pin and ground. Once the VCC reaches 9V, the internal switch stops charging the capacitor. SenseFET Drain. The drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
2
Vcc
3
Vfb
4
NC
5
Vstr
6,7,8
Drain
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25C, unless otherwise specified.
Symbol
VDRAIN VSTR VDG VGS VCC VFB PD TJ TA TSTG Drain Pin Voltage Vstr Pin Voltage Drain-Gate Voltage Gate-Source Voltage Supply Voltage
Parameter
Value
650 650 650 20 20 -0.3 to VSTOP 1.40 Internally limited -25 to +85 -55 to +150
Unit
V V V V V V W C C C
Feedback Voltage Range Total Power Dissipation Operating Junction Temperature Operating Ambient Temperature Storage Temperature
Notes: 1. Repetitive rating: Pulse width is limited by maximum junction temperature. 2. L = 24mH, starting TJ = 25C.
Thermal Impedance
TA = 25C, unless otherwise specified. All items are tested with the JEDEC standards JESD 51-2 and 51-10 (DIP).
Symbol
JA JC
Parameter
Junction-to-Ambient Thermal Impedance Junction-to-Case Thermal Impedance(4)
(3)
Value
88.84 13.94
Unit
C/W C/W
Notes: 3. Free-standing with no heatsink; without copper clad. Measurement condition - just before junction temperature TJ enters into OTP. 4. Measured on the DRAIN pin close to plastic interface.
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Electrical Characteristics
TA = 25C, unless otherwise specified.
Symbol
SenseFET Section IDSS RDS(ON) gfs CISS COSS CRSS fOSC fOSC DMAX VSTART VSTOP IFB tS/S VBURH VBURL VBUR(HYS) Protection Section ILIM TSD VSD VOVP IDELAY IOP ICH
Parameter
Conditions
VDS=650V, VGS=0V
VDS=520V, VGS=0V, TC=125C
Min.
Typ.
Max.
25 200
Unit
Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance(5) Forward Trans-Conductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Frequency Switching Frequency Variation Maximum Duty Cycle UVLO Threshold Voltage Feedback Source Current Internal Soft Start Time
(6)
A S pF
VGS=10V, ID=0.5A VDS=50V, ID=0.5A VGS=0V, VDS=25V, f=1MHz 1.0
16 1.3 162 18 3.8 61 67 5 60 67 9 7 0.40 15 0.7 0.55 150 0.475 0.550 145 4.5 5 1.5 450 550 8 6 0.35 10 0.6 0.45
22
Control Section 73 10 74 10 8 0.45 20 0.8 0.65 kHz % % V V mA ms V V mV 0.650 5.0 6 3.0 650 A C V V A mA A -25C TA 85C VFB=GND VFB=GND 0V VFB 3V
Burst Mode Section Burst Mode Voltage TJ=25C Hysteresis Peak Current Limit Thermal Shutdown Temperature Shutdown Feedback Voltage Over-Voltage Protection Shutdown Delay Current Operating Supply Current (8) Start-Up Charging Current 3V VFB VSD VCC 16V VCC=0V , VSTR=50V
(7)
125 4.0 20 4
Total Device Section
Notes: 5. Pulse test: Pulse width 300s, duty 2%. 6. These parameters, although guaranteed, are tested in EDS (wafer test) process. 7. These parameters, although guaranteed, are not 100% tested in production. 8. Control part only.
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25C.
1.15 1.10 1.05
1.15 1.10 1.05
VOVP
0.95 0.90 0.85 -50 0 50 100 150
IOP
1.00
1.00 0.95 0.90 0.85 -50 0 50 100 150
Temperature [C]
Temperature [C]
Figure 4.
Over-Voltage Protection (VOVP) vs. TA
Figure 5.
Operating Supply Current (IOP) vs. TA
1.15 1.10 1.05
1.15 1.10 1.05
VSTAART
1.00 0.95 0.90 0.85 -50 0 50 100 150
VSTOP
1.00 0.95 0.90 0.85 -50 0 50 100 150
Temperature [C]
Temperature [C]
Figure 6.
Start Threshold Voltage (VSTART) vs. TA
Figure 7.
Stop Threshold Voltage (VSTOP) vs. TA
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -50 0 50 100 150
1.15 1.10 1.05
DMAX
fOSC
1.00 0.95 0.90 0.85 -50 0 50 100 150
Temperature [C]
Temperature [C]
Figure 8.
Operating Frequency (fOSC) vs. TA
Figure 9.
Maximum Duty Cycle (DMAX) vs. TA
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA = 25C.
1.15 1.10 1.05
1.15 1.10 1.05
ILIM
1.00 0.95 0.90 0.85 -50 0 50 100 150
IFB
1.00 0.95 0.90 0.85 -50 0 50 100 150
Temperature [C]
Temperature [C]
Figure 10.
Peak Current Limit (ILIM) vs. TA
Figure 11.
Feedback Source Current (IFB) vs. TA
1.15 1.10 1.05
1.15 1.10 1.05
IDELAY
1.00 0.95 0.90 0.85 -50 0 50 100 150
VSD
1.00 0.95 0.90 0.85 -50 0 50 100 150
Temperature [C]
Temperature [C]
Figure 12.
Shutdown Delay Current (IDELAY) vs. TA
Figure 13. Shutdown Feedback Voltage (VSD) vs. TA
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Functional Description
1. Start-up: At start-up, the internal high-voltage current source supplies the internal bias and charges the external VCC capacitor, as shown in Figure 14. When VCC reaches 9V, the device starts switching and the internal high-voltage current source stops charging the capacitor. The device is in normal operation provided VCC does not drop below 7V. After start-up, the bias is supplied from the auxiliary transformer winding.
VIN ,dc ISTR
VO Vfb Cfb
4 + R
When the shunt regulator reference pin voltage exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, the feedback voltage VFB is pulled down, and it reduces the duty cycle. This happens when the input voltage increases or the output load decreases.
VCC 5A
Vref
400A
OSC
Gate
driver
Vstr V CC
L
V fb
H
KA431
VSD
OLP
9V/ 7V
Figure 16. Figure 14. Internal Start-up Circuit
PWM and Feedback Circuit
Calculating the VCC capacitor is an important step to design with the FSQ100. At initial start-up, the maximum value of start operating current ISTART is about 100A, which supplies current to UVLO and VREF blocks. The charging current IVCC of the VCC capacitor is equal to ISTR - 100A. After VCC reaches the UVLO start voltage, only the bias winding supplies VCC current to the device. When the bias winding voltage is not sufficient, the VCC level decreases to the UVLO stop voltage and the internal current source is activated again to charge the VCC capacitor. To prevent this VCC fluctuation (charging/discharging), the VCC capacitor should be chosen to have a value between 10F and 47F.
VIN ,dc IVcc = ISTR-ISTART IVcc = ISTR-ISTART V CC ISTART ISTR Vstr J-FET
3. Leading Edge Blanking (LEB): At the instant the internal SenseFET is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically causes a high-current spike through the SenseFET. Excessive voltage across the RSENSE resistor lead to incorrect pulse-by-pulse current limit protection. To avoid this, a leading edge blanking (LEB) circuit disables pulse-by-pulse current-limit protection block for a fixed time (tLEB) after the SenseFET turns on. 4. Protection Circuit: The FSQ100 has protective functions, such as overload protection (OLP), over voltage protection (OVP), under-voltage lockout (UVLO), and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, reliability is improved without increasing costs. Once a fault condition occurs, switching is terminated and the SenseFET remains off. This causes VCC to fall. When VCC reaches the UVLO stop voltage VSTOP (7V), the protection is reset and the internal highvoltage current source charges the VCC capacitor via the Vstr pin. When VCC reaches the UVLO start voltage VSTART (9V), the device resumes normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated.
UVLO Vref
VCC
V START
UVLO
VCC must not drop below VSTOP
OSC
VSTOP Bias winding voltage t
5 A V fb C fb
RESET 4
400A
+ -
SQ R
GATE DRIVER
R OLP SQ 4.5V TSD R
A /R
Figure 15.
Charging VCC Capacitor through Vstr
OLP, TSD Protection Block
2. Feedback Control: The FSQ100 is a voltage mode controlled device, as shown in Figure 16. Usually, an opto-coupler and shunt regulator, like KA431 are used to implement the feedback network. The feedback voltage is compared with an internally generated sawtooth waveform. This directly controls the duty cycle.
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1 8
Figure 17.
Protection Block
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
4.1 Overload Protection (OLP): Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS is operating normally, the over load protection (OLP) circuit can be activated during the load transition. To avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or a true overload situation. If the output consumes more than the maximum power determined by ILIM, the output voltage (VO) decreases below its rating voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 3V, the feedback input diode is blocked and the 5A current source (IDELAY) starts to charge CFB slowly up to VCC. In this condition, VFB increases until it reaches 4.5V, when the switching operation is terminated, as shown in Figure 18. The shutdown delay time is the time required to charge CFB from 3V to 4.5V with a 5A current source.
VFB Overload Protection 4.5V
Drain current 0.55A 2.14ms 7steps 0.31A
t
Figure 19.
Internal Soft-Start
6. Burst Operation: To minimize the power dissipation in standby mode, the FSQ100 enters burst-mode operation. As the load decreases, the feedback voltage decreases. The device automatically enters burst mode when the feedback voltage drops below VBURL (0.55V). At this point, switching stops and the output voltages start to drop. This causes the feedback voltage to rise. Once is passes VBURH (0.70V), switching starts again. The feedback voltage falls and the process repeats. Burst-mode operation alternately enables and disables switching of the power MOSFET to reduce the switching loss in standby mode.
OSC GATE DRIVER on /off
3V
V fb 4
S 5A 400A R
Q
t12 = Cfbx(V(t2 )-V(t1 )) / IDELAY
t1
t12 = Cfb
t2
t
0.70V /0.55V Burst Operation Block
V (t2 ) -V (t1) ; I DELAY = 5A, V (t1) = 3V , V (t2 ) = 4.5V I DELAY
Figure 20.
VO
VO set
Burst Operation Block
Figure 18.
Overload Protection (OLP)
4.2 Thermal Shutdown (TSD): The SenseFET and the control IC are integrated, making it easier for the control IC to detect the temperature of the SenseFET. When the temperature exceeds approximately 145C, thermal shutdown is activated. 5. Soft-Start: The FPS has an internal soft-start circuit that slowly increases the feedback voltage, together with the SenseFET current, right after it starts. The typical soft-start time is 15ms, as shown in Figure 19, where progressive increment of the SenseFET current is allowed during the start-up phase. Soft-start circuit progressively increases current limits to establish proper working conditions for transformers, inductors, capacitors, and switching devices. It also helps to prevent transformer saturation and reduces the stress on the secondary diode.
VFB
0.70V 0.55V
Ids
Vds
t
Figure 21.
Burst Operation Function
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 -- Green Mode Fairchild Power Switch (FPSTM)
Application Tips
1. Methods of Reducing Audible Noise Switching mode power converters have electronic and magnetic components that generate audible noise when the operating frequency is in the range of 20~20,000Hz. Even though they operate above 20kHz, they can make noise, depending on the load condition. Designers can employ several methods to reduce noise. Glue or Varnish The most common method involves using glue or varnish to tighten magnetic components. The motion of core, bobbin and coil, and the chattering or magnetostriction of core can cause the transformer to produce audible noise. The use of rigid glue and varnish helps reduce the transformer noise, but can crack the core. This is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio. Ceramic Capacitor Using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise-reduction solution. Some dielectric materials show a piezoelectric effect, depending on the electric field intensity. Hence, a snubber capacitor becomes one of the most significant sources of audible noise. It is possible to use a Zener clamp circuit instead of an RCD snubber for higher efficiency as and lower audible noise. Adjusting Sound Frequency Moving the fundamental frequency of noise out of 2~4kHz range is the third method. Generally, humans are more sensitive to noise in the range of 2~4kHz. When the fundamental frequency of noise is located in this range, the noise is perceived as louder, although the noise intensity level is identical (refer to Figure 22 Equal Loudness Curves). When FPS acts in burst mode and the burst operation is suspected to be a source of noise, this method may be helpful. If the frequency of burst-mode operation lies in the range of 2~4 kHz, adjusting the feedback loop can shift the burst operation frequency. To reduce the burst operation frequency, increase a feedback gain capacitor (CF), opto-coupler supply resistor (RD), and feedback capacitor (CB); and decrease a feedback gain resistor (RF), as shown in Figure 23. Figure 23. Typical Feedback Network of FPSTM
Figure 22.
Equal Loudness Curves
2. Reference Materials AN-4134: Design Guidelines for Off-line Forward TM Converters Using Fairchild Power Switch (FPS ) AN-4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPSTM) AN-4138: Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPSTM) AN-4140: Transformer Design Consideration for Off-line Flyback Converters Using Fairchild Power Switch (FPSTM) AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147: Design Guidelines for RCD Snubber of Flyback AN-4148: Audible Noise Reduction Techniques for FPSTM Applications
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 Green Mode Fairchild Power Switch (FPSTM)
Physical Dimensions
Dimensions are in millimeters and inches unless otherwise noted.
Figure 24.
8-Pin Dual Inline Package (DIP)
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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FSQ100 Green Mode Fairchild Power Switch (FPSTM)
(c) 2007 Fairchild Semiconductor Corporation FSQ100 Rev. 1.0.1
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